The present disclosures relate to integrated circuit manufacturing, and more particularly, to a primitive cell method for front end physical design for integrated circuit manufacturing.
Problems exist in the current designing and building of electronic systems in integrated circuits. These problems include, but are not limited to, (1)complex front-end design rules, (2) complexity and inaccuracy of translating written design rules into Design Rule Check (DRC) code, (3) difficulty or impossibility to achieve one hundred percent (100%) coverage with DRC Quality Assurance (QA) cells, (4) an inability of layout designers to comprehend written rules, wherein a corresponding layout is performed by trial-and-error, and layout checking is performed with (imperfect) DRC decks that correspond to machine readable code of the design rules, (5) an inaccuracy of front-end device models with respect to silicon due to small layout variations, (6) transistor variability on chip due to randomness in physical design, (7) 65 nm and beyond process requires post-layout extraction to comprehend non-local effects (stressors, etc.) on front-end device models, and (8) irregular front-end layout practices complicate the generation of derived layers (e.g., stressor films), and create unexpected flaws such as slivers/gaps.
With current layout design proposals, variations in layout style increase variability in device electrical behavior. Neighboring structures within the layout have an increasing effect on electrical behavior and complicates modeling. Current methods to comprehend these effects require the use of very complex post-layout extraction to back annotate models for simulation. Even with the post layout extraction, the ability of the models to accurately represent the electrical behavior of all devices is poor. Furthermore, design rules are increasing in complexity so rapidly that existing paradigms cannot continue to handle them.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.